1. Field of the Invention
The invention relates generally to semiconductor devices, and more particularly, toward redundancy circuits within programmable arrays of semiconductor devices and operating methods therefor. The invention is particularly useful for providing circuit redundancy within semiconductor memory arrays.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a structure of a conventional semiconductor memory device provided with a redundant circuit. FIG. 1 shows an example of a 64K bit-dynamic random access memory (DRAM) having eight inputs A.sub.0 to A.sub.7 as address inputs. The redundant circuit is a spare circuit for improving the production yield, comprising a spare memory cell, a spare decoder and so on.
Referring to FIG. 1, the memory cell array 1 comprises a plurality of memory cells arranged in a plurality of rows and columns. The memory cell array 1 comprises a spare row 2 constituted by spare memory cells arranged in a plurality of rows and a spare column 3 constituted by spare memory cells arranged in a plurality of columns. A plurality of word lines are provided corresponding to the plural rows of the memory cell array 1 and a plurality of bit lines are provided corresponding to the plural columns of the same.
Meanwhile, a RAS buffer 4 activates a row address buffer 5, .phi..sub.p generation circuit 6, .phi..sub.x generation circuit 7 and a sense amplifier control circuit 8 in response to an externally applied row address strobe signal RAS. The .phi..sub.p generation circuit 6 and the .phi..sub.x generation circuit 7 generate a precharge signal .phi..sub.p and a driving signal .phi..sub.x at prescribed timings, respectively. The row address buffer 5 latches externally applied address signals A.sub.0 to A.sub.7 and applies a part of the signals as row address signals RA.sub.2 to RA.sub.7 to the row predecoder 9 and applies the remainder as row address signals RA.sub.0 to RA.sub.1 to the 140 x subdecoder 10. The row predecoder 9 predecodes row address signals RA.sub.2 to RA.sub.7 applied from the row address buffer 5 and applies row selection signals X.sub.i, X.sub.j and X.sub.k to the row decode group 11 and to the spare row decoder 12. The row decoder group 11 selects four rows in the memory cell array 1 in response to the row selection signals X.sub.i, X.sub.j and X.sub.k. The .phi..sub.x subdecoder 10 applies subdecode signals .phi..sub.x1 to .phi..sub.x4 to the word driver group 13 in response to the driving signal .phi..sub.x from the .phi..sub.x generation circuit 7 based on the row address signals RA.sub.0 to RA.sub.1 applied from the row address buffer 5. The word driver group 13 drives word lines for one row out of the four rows selected by the row decoder group 11 or by the spare row decoder 12 in response to the subdecode signals .phi..sub.x1 to .phi..sub.x4. The sense amplifier control circuit 8 operates the sense amplifier group 14 at a prescribed timing. The sense amplifier group 14 amplifies the information on each bit line.
Meanwhile, the CAS buffer 15 activates a column address buffer 16 and a read/write buffer 17 in response to an externally applied column address strobe signal CAS. The column address buffer 16 latches externally applied address signals A.sub.0 to A.sub.7 and applies the same to the column predecoder 18 as the column address signals. The column predecoder 18 predecodes the column address signals and applies column selection signals to the column decoder group 19 and to a spare column decoder 20. The column decoder group 19 selects one column in the memory cell array 1 based on the column selection signal. In this manner, one word line and one bit line are selected and reading or writing of information is carried out for the memory cell at the intersection. In FIG. 1, only the selected one word line WL, thee selected one bit line BL and a memory cell MC at the intersection thereof are shown.
The reading or writing of the information is selected by the read/write buffer 17. The read/write buffer 17 activates an input buffer 21 or an output buffer 22 in response to an externally applied read/write signal R/W. When the input buffer 21 is activated, the input data D.sub.IN is written in the memory cell MC which is selected as described above. When output buffer 22 is activated, the information stored in the memory cell MC which is selected as described above is read as the output data D.sub.OUT. Each of the above described circuits is formed on the same semiconductor chip 23.
Meanwhile, sometimes defective memory cells are generated in the process of manufacturing. There are some defective word lines such as snapped ones. If the defects are generated only in some portions, it is economically unpreferable to regard the whole semiconductor memory device formed on the semiconductor chip as a defective. Therefore, it is set beforehand that if a defective memory cell or a defective word line is included in the selected row, a spare row 2 is selected instead of the defective row by the spare row decoder 12. In addition, it is set beforehand that if a defective memory cell or a defective bit line is included in the selected column, a spare column 3 is selected instead of the defective column by the spare column decoder 20. In this manner, the production yield is improved.
FIG. 2 shows a structure of one portion of the row predecoder included in FIG. 1, illustrating the circuit portion for generating the row selection signal X.sub.i. X.sub.i denotes one of the signals X.sub.1, X.sub.2, X.sub.3 and X.sub.4.
A gate circuit 91 receives the row address signal RA.sub.2 and outputs the same signal RA.sub.2 and the inverted signal RA.sub.2 of the row address signal RA.sub.2. A gate circuit 92 receives the row address signal RA.sub.3 and outputs the same signal RA.sub.3 and the inverted signal RA.sub.3 of the row address signal RA.sub.3. Either the signal RA.sub.2 or RA.sub.2 and either the signal RA.sub.3 or RA.sub.3 are inputted to the gate circuits 93, 94, 95 and 96, respectively. The combination of the signals RA.sub.2 or RA.sub.2 and RA.sub.3 inputted to the gate circuits 93 to 96 is different from each other. Row selection signals X.sub.1 to X.sub.4 are outputted from the gate circuits 93 to 96, respectively. One of the row selection signals X.sub.1 to X.sub.4 becomes "H" level and other signals become "L" level in response to the levels of the row address signals RA.sub.2 and RA.sub.3.
The row selection signal X.sub.j in FIG. 1 means one of the signals X.sub.5, X.sub.6, X.sub.7 and X.sub.k means one of the signals X.sub.9, X.sub.10, X.sub.11 and X.sub.12. The row selection signals X.sub.5 to X.sub.8 are generated in the similar manner as FIG. 2 by the row address signals RA.sub.4 and RA.sub.5, while the row selection signals X.sub.9 to X.sub.12 are generated in the similar manner as FIG. 2 by the row address signals RA.sub.6 and RA.sub.7.
FIG. 3 shows the structure of .phi..sub.x subdecoder 10 included in FIG. 1. The .phi..sub.x1 generation circuit 101, .phi..sub.x2 generation circuit 102, .phi..sub.x3 generation circuit 103 and .phi..sub.x4 generation circuit 104 respectively receive the row address signal RA.sub.0 or the inversion signal RA.sub.0 and the row address signal RA.sub.1 or the inversion signal RA.sub.1 and output subdecode signals .phi..sub.x1, .phi..sub.x2, .phi..sub.x3 and .phi..sub.x4 in response to the driving signal .phi..sub.x. One of the subdecode signals .phi..sub.x1, .phi..sub.x2, .phi..sub.x3 and .phi..sub.x4 becomes "H" level and others become "L" level in response to the levels of the row address signals RA.sub.0, RA.sub.1 and of the inversion signals RA.sub.0, RA.sub.1.
FIG. 4 shows a detailed structure of the memory cell array 1 and the peripheral portion thereof included in FIG. 1.
4m word lines WL and a plurality of bit line pairs BL and BLare arranged intersecting with each other in the memory cell array 1, where m is a positove integer. Four spare word lines SWL are arranged on the side of the word lines WL. A memory cell MC is provided at an intersection of each word line WL and the bit line BL or BL, while a spare memory cell SMC is provided at an intersection of each spare word line SWL and the bit line BL or BL. (4m+4( word drivers 13a are provided corresponding to 4m word lines WL and 4 spare word lines SWL. Each of the word lines WL and each of the spare word lines SWL is connected to the corresponding word driver 13a. 4m word lines WL and 4m word drivers 13a are divided into m sets, each comprising four word lines WL and four word drivers 13a. m row decoders 11a are provided corresponding to the m sets. Each row decoder 11a selects four word drivers 13a of the corresponding set. One spare row decoder 12 is provided corresponding to four spare word lines SWL and four word drivers 13a. The spare row decoder 12 selects four corresponding word drivers 13a.
A plurality of sense amplifiers 14a and a plurality of column decoders 19a are provided corresponding to a plurality of bit line pairs BL and BL. Each bit line pair BL and BL is connected to the corresponding sense amplifier 14a and the corresponding column decoder 19a.
The operation of the circuit shown in FIG. 4 will be described in the following.
One of the row decoders 11a is selected based on the row selection signals X.sub.i, X.sub.j and X.sub.k. The selected row decoder 11a drives four word drivers 13a of the corresponding set. One of the four word drivers 13a drives the corresponding word line WL in response to the subdecode signals .phi..sub.x1 to .phi..sub.x4. Consequently, the information in the memory cell MC connected to the word line WL is read onto each bit line BL or BL and is amplified by the sense amplifier 14a. One of the column decoders 19a is selected in response to the column address signal. In writing, the information is written onto the bit line pair BL and BL connected to the selected column decoder 19a. In reading, the information on the bit line pair BL and BL connected to the selected column decoder 19a is read.
When a defective memory cell or a defective word line is formed in the process of manufacturing, a spare row decoder 12 is selected instead of the row decoder 11a which is in correspondence with the defective memory cell or the defective word line. More specifically, when an address signal is applied to select the row decoder 11a corresponding to the defective memory cell or the defective word line, the spare row decoder 12 is selected instead of the row decoder 11a. One of the word drivers 13a connected to the spare row decoder 12 drives the corresponding spare word line SWL in response to the subdecode signals .phi..sub.x1 to .phi..sub.x4.
FIG. 5 shows definite circuit structure of the row decoder 11a and the word driver 13a shown in FIG. 4.
The row decoder 11a comprises N channel MOS transistors Q1 to Q4, P channel MOS transistors Q5 to Q7 and a linking device LNO. The linking device LNO is formed of polycrystalline silicon, aluminum or the like and it can be blown out by a laser beam or the like. The transistors Q5 and Q6 are coupled between the supply potential V.sub.CC and a node N1. A precharge signal .phi..sub.p is applied to the gate of the transistor Q5 and the gate of the transistor Q6 is connected to a node N2. The linking device LNO and the transistors Q1, Q2 and Q3 are coupled in series between the node N1 and the ground potential. Row selection signals X.sub.1, X.sub.j and X.sub.k are respectively applied to the gates of the transistors Q1, Q2 and Q3. As described above, X.sub.i denotes one of X.sub.1 to X.sub.4, X.sub.j denotes one of X.sub.5 to X.sub.8 and X.sub.k denotes one of X.sub.9 to X.sub.12. The combination of the row selection signals X.sub.i, X.sub.j and X.sub.k applied to each row decoder 11a differs from that of other row decoders 11a. The transistor Q7 is coupled between the supply potential V.sub.CC and the node N2 and its gate is connected to the node N1. The transistor Q4 is coupled between the node N2 and the ground potential, and its gate is connected to the node N1. The transistors Q4 and Q7 constitute an inverter. Therefore, the level of the node N2 and the level of the node N1 are opposite to each other. When a defect exists in the memory cell or in the word line, the linking device LNO of the corresponding row decoder 11a is blown out beforehand by the laser beam.
The nodes N1 and N2 of each row decoder 11a are connected to the four word drivers 13a of the corresponding set. Each word driver 13a comprises N channel MOS transistors Q8, Q9 and Q10. The transistor Q9 is coupled between one of the subdecode signals .phi..sub.xl to .phi..sub.x4 and a word line WL and its gate is connected to the node N2 of the corresponding row decoder 11a through the transistor Q8. The transistor Q10 is coupled between the word line WL and the ground potential and its gate is connected to the node N1 of the corresponding row decoder 11a. The gate of the transistor Q8 is coupled to the supply potential V.sub.CC. Word drivers 13a in each set are coupled to respective different ones of the subdecode signals .phi..sub.x1, .phi..sub.x2, .phi..sub.x3 and .phi..sub.x4.
Next, the operation of the row decoder 11a and the word driver 13a will be described in the following. When the precharge signal .phi..sub.p is at the "L" level, the transistor Q5 is in the on state and the potential of the node N1 is at the "H" level (V.sub.CC level). Therefore, the transistor Q10 of the word driver 13a is in the on state and the potential of the word line WL is at the "L" level (ground level). When the precharge signal .phi..sub.p rises to the "H" level, the transistor Q5 turns off. When row selection signals X.sub.i, X.sub.j and X.sub.k applied to the gates of the transistors Q1, Q2 and Q3 all become "H" level, the transistors Q1, Q2 and Q3 all turn on, so that the potential of the node N1 becomes "L" level and the potential of the node N2 becomes "H" level. Consequently, the transistor Q10 of the word driver 13a turns off. When one of the subdecode signals .phi..sub.x1 to .phi..sub.x4 rises to the "H" level, the potential of the corresponding word line WL rises to the "H" level. However, if the linking device LNO was blown out, the potential of the node N1 remains "H" level, so that the potential of the word line WL is kept at the "L" level. Therefore, when the linking device LNO was blown out beforehand, the four word lines WL corresponding to the row decoder 11a are not selected.
FIG. 6 shows a concrete circuit structure showing a spare row decoder 12 included in FIG. 4.
The spare row decoder 12 comprises N channel MOS transistors Q11 to Q25, P channel MOS transistors Q26 to Q30 and linking devices LN1 to LN2. The transistors Q29 and Q30 are coupled in parallel between the supply potential V.sub.CC and a node N3. The transistors Q11 to Q22 are coupled between teh node N3 and the ground potential through the linking devices LN1 to LN12, respectively. The gates of the transistors Q11 to Q22 are coupled to the row selection signals X.sub.1 to X.sub.12, respectively. The transistors Q26 and Q27 are coupled in parallel between the supply potential V.sub.CC and the node N1. The transistors Q23 and Q24 are coupled in series between the node N1 and the ground potential. Precharge signals .phi..sub.p are applied to the gate of the transistors Q26, Q23 and Q29. The gates of the transistors Q27 and Q24 are connected to the node N3. The transistor Q28 is coupled between the supply potential V.sub.CC and the node N2 and the transistor Q25 is coupled between the node N2 and the ground potential. Gates of the transistors Q28, Q25 and Q30 are connected to the node N1. The transistors Q23, Q24, Q26 and Q27 constitute a two-input NAND gate and the transistors Q25 and Q28 constitute an inverter.
In order to select a spare row decoder 12 instead of a certain row decoder 11a, a linking device out of the linking devices LN1 to LN12 which corresponds to the row decoder 11a is blown out previously. For example, let us assume that the spare decoder 12 should be selected instead of the row decoder 11a shown in FIG. 6. When the linking device LNO is not blown out, the shown row decoder 11a is selected when the row selection signals X.sub.1, X.sub.5 and X.sub.9 all become "H" level. Therefore, the linking device LNO of the row decoder 11a and the linking devices LN1, LN5 and LN9 of the spare row decoder 12 are blown out previously.
When the precharge signal .phi..sub.p is at the "L" level, the transistor Q26 is in the on state, the transistor Q23 is in the off state and the node N1 is precharged to the "H" level. Therefore, the node N2 is at the "L" level. On this occassion, since the transistor Q29 is in the on state, the node N3 is precharged to the "H" level, so that the transistor Q27 is in the off state and the transistor Q24 is in the on state. When the precharge signal .phi..sub.p rises to the "H" level, the transistor Q26 turns off and the transistor Q23 turns on. Therefore, the potential of the node N1 becomes "L" level and the potential of the node N2 becomes "H" level. At this time, the transistor Q29 turns off and the transistor Q30 turns on. When the row selection signals X.sub.1, X.sub.5 and X.sub.9 all become "H" level, the transistors Q11, Q15 and Q19 turn on. However, since the linking devices LN1, LN5 and LN9 connected to these transistors Q11, Q15 and Q19 have been cut, the potential of the node N3 is maintained at the "H" level. Therefore, the potential of the node N1 remains at the "L" level and the potential of the node N2 remains at the "H" level. This state means that the spare row decoder 12 is selected.
When at least one of the row selection signals other than the signals X.sub.1, X.sub.5 and X.sub.9 becomes "H" level, then at least one transistor other than the transistors Q11, Q15 and Q19 turns on, so that the potential of the node N3 becomes "L" level. Consequently, the transistor Q27 turns on and the transistor Q24 turns off, and, as a result, the node N1 becomes "H" level and the node N2 becomes "L" level. This state means that the spare row decoder 12 is not selected. In this manner, when the linking devices LN1, LN5 and LN9 are cut, the spare row decoder 12 is selected instead of the row decoder 11a when the row selection signals X.sub.1, X.sub.5 and X.sub.9 become "H" level.
The operation of the semiconductor memory device shown in FIGS. 1 to 6 will be described with reference to the timing chart of FIG. 7.
In the standby period when the precharge signal .phi..sub.p is at the "L" level, the potential of the nodes N1 is at the "H" level and the potential of the nodes N2 is at the "L" level for all row decoders 11a and the spare row decoder 12. Therefore, the potential of all word lines WL and all spare word lines SWL is at the "L" level.
The row decoder 11a corresponding to normal memory cells MC and normal four word lines WL (hereinafter referred to as a normal decoder) is selected. After the precharge signal .phi..sub.p rises to the "H" level, the signals X.sub.i, X.sub.j and X.sub.k applied to the selected row decoder 11a all become "H" level. Therefore, the potential of the node N1 falls to the "L" level and the potential of the node N2 rises to the "H" level. Consequently, the corresponding four word drivers 13a are selected. When one of the subdecode signals .phi..sub.x1 to .phi..sub.x4 rises to the "H" level, the potential of the corresponding word line WL is raised to the "H" level by the word driver 13a. At this time, the potential of the spare word line SWL remains at the "L" level.
Description will be given of a case in which a row decoder 11a (hereinafter referred to as a defective decoder) corresponding to a defective memory cell MC or a defective word line WL is selected. After the precharge signal .phi..sub.p rises to the "H" level, the row selection signals X.sub.i, X.sub.j and X.sub.k which are to be applied to the selected defective decoder 11a all become "H" level. However, the linking device LNO of the defective decoder 11a has been blown out previously, so that the potential of the node N1 remains at the "H" level and the potential of the node N2 remains at the "L" level. Therefore, the four word drivers 13a corresponding to the defective decoder 11a are not selected so that the potential of the corresponding word line WL remains at the "L" level even if one of the subdecode signals .phi..sub.x1 to .phi..sub.x4 rises to the "H" level. At this time, the spare row decoder 12 is selected instead of the defective decoder 11a and, as a result, one of the spare word lines SWL rises to the "H" level. In the above described case, in the row decoders 11a which are not selected by the address signals (non-selected decoders), at least one of the applied row selection signals X.sub.i, X.sub.j and X.sub.k maintains "L" level, so that the potential of the node N1 remains at the "H" level and the potential of the node N2 remains at the "L" level. Therefore, the potential of the corresponding word lines WL is maintained at the "L" level.
As described above, even if a defective memory cell or a defective word line is generated in the process of manufacturing, the defective decoder can be replaced by a spare decoder, so that it can be used as a normal semiconductor memory device.
In the above described semiconductor memory device, when a defect such as a defect in the memory cell (bit defect), snapping of word line, short circuit of the word line in the same row decoder is generated, the defect can be compensated for by replacing the corresponding row decoder with a spare row decoder. For example, as shown in FIG. 8, the snapping (shown by d1) of the word line WL corresponding to the row decoder 11a-j or a short circuit (shown by d2) between word lines WL corresponding to the row decoder 11a-j can be compensated for. However, if a defect such as a short circuit between word lines corresponding to different row decoders, the defects remain even when the replacement of one spare row decoder is effected. For example, a short circuit (shown by d3) between the word line belonging to the row decoder 11a-j and the word line belonging to the row decoder 11a-k can be compensated for only by providing two spare row decoders. Such problem seems to become more serious as the memory devices have been implemented with larger capacities and the devices have been made more minute.
One object of the invention is to provide semiconductor devices wherein various defects therein detected during manufacture can be corrected.
Another object of the invention is to provide improved circuit redundancy within programmable arrays of semiconductor components, wherein large defects can be corrected.
Another object is to provide, within a programmable array of semiconductor components that can be addressed by line decoders each for selecting among a predetermined number of signal lines, improved circuit redundancy wherein short ciruits between signal lines of different line decoders can be corrected.
A further object of the invention is to provide circuit redundancy within semiconductor memory arrays, wherein the group of word lines belonging to a row decoder to be replaced by a spare decoder can be varied.
A further object of the invention is to provide, within a semiconductor memory device of a type having an array of memory cells arranged at intersections of bit lines and word lines, wherein row decoders select among predetermined numbers of different word lines and column decoders select among predetermined numbers of different bit line, improved circuit redundancy wherein short circuits between word lines of different row decoders can be corrected.
A still further object is to substantially enhance production yield of semiconductor device arrays by correcting various defects produced in the process of manufacturing the arrays.
An additional object of the invention is to provide improved circuit redundancy within semiconductor dynamic random access memories.
The semiconductor memory device in accordance with the present invention is a semiconductor memory device having a redundant circuit, comprising: a plurality of selection lines; a plurality of spare selection lines; a plurality of memory cells each of which connected to any one of the plurality of selection lines; and a plurality of spare memory cells each of which is connected to any one of the plurality of spare selection lines. The plurality of selection lines are divided into a plurality of first sets each comprising prescribed plurality of selection lines and are divided into a plurality of second sets each comprising a presecribed plurality of selection lines. The semiconductor memory device comprises a plurality of selection means, spare selection means and switching means. Each of the selection means is selectively coupled to the plurality of selection lines of each of the first sets or to the plurality of selection lines of each of the second sets and is activated in response to a prescribed selection signal for selecting the selection lines in each of the first sets or the selection lines of each of the second sets. The spare selection means is coupled to the plurality of spare selection lines and is activated instead of any one of the selection means to select the plurality of spare selection lines. The switching means is to selectively couple each selection means to the plurality of selection lines in each of the first sets or to the plurailty of selection lines in each of the second sets.
According to the semiconductor device of the present inventon, since each selection means can be selectively connected to the plurality of selection lines in each of the first sets or to the plurality of selection lines in each of the second sets by the switching means, when a defect is generated over a plurality of selection lines, the state of coupling of the plurality of selection lines and the selection means can be switched so that the defective selection lines are coupled to one selection means. Therefore, by replacing the selection means coupled to the defective selection lines with one spare selection means, the defects over a plurality of selection lines can be repaired.
In accordance with another aspect of the present invention, a system for repairing defects in a semiconductor device formed of an array of semiconductor components arranged at intersections of rows and columns, and including pluralities of address decoder means for selecting the components in response to external row and column address signals, each decoder means connected to a different group of address lines, and redundancy circuit means comprising a spare decoder means, a plurality of spare address lines connected to the spare decoder means, and a plurality of spare semiconductor components connected to the plurality of spare address lines, comprising: means for measuring the semiconductor device to detect defects therein; means for identifying particular decoder means associated with the defects; means for determining whether the defects detected during the measuring step extend between address lines connected to different particular decoder means, and, in response; means for changing the group of address lines connected to the one of the particular decoder means; and means for replacing the one of the particular decoder means by the spare decoder means.
In accordance with further aspect of the present invention, in a semiconductor device formed of an array of semiconductor components arranged at intersections of rows and columns, and including pluralities of address decoder means for selecting the components in response to external row and column address signals, each decoder means connected to a different group of address lines, and redundancy circuit means comprising a spare decoder means, a plurality of spare address lines connected to the spare decoder means, and a plurality of spare semiconductor components connected to the plurality of spare addres lines; a method of correcting defects in the semiconductor device, comprising the steps of: measuring the semiconductor device to detect defects therein; identifying particular decoder means associated with the defects; determining whether the defects detected during the measuring step extend between address lines connected to different particular decoder means, and, in response; changing the group of address lines connected to the one of the particular decoder means; and replacing the one of the particular decoder means by the spare decoder means.
These objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompany drawings.